Digit-serial linear combining apparatus

ABSTRACT

Linear combining apparatus for digit-serial data performs addition, subtraction and comparison functions on a systolic basis. Signals are afforded the apparatus indicating the occurence of the most significant digits of the digit-serial signals being linearly combined.

This is a continuation-in-part of U.S. Pat. application Ser. No. 265,210 filed 31 Oct. 1988, now U.S. Pat. No. 5,010,511 issued, which is a continuation-in-part of U.S. Pat. application Ser. No. 182,602 filed 18 Apr. 1988, now U.S. Pat. No. 4,951,221 issued 21 Aug. 1990.

The invention relates to combining apparatus as may perform, on a pipelined basis, addition and subtraction processes. More particularly, the invention relates to pipe-lined linear combining apparatus for performing these processes on digit-serial data.

BACKGROUND OF THE INVENTION

Digital signals having words of a number W of bits may be subjected to parallel processing, serial processing, or processing that combines features of parallel and serial processing. Parallel processing of the W-bit words wherein the W bits flow in respective bit streams for simultaneous individual processing allows relatively high rates of processing with relatively low latency. However, processing circuitry is in large part replicated W-fold with attendant cost in terms of operating power and digital hardware. In monolithic integrated circuit constructions, more die area is consumed because of the increased hardware requirements. Serial prccessing, wherein the W bits of each word are sequentially processed, does not require W-fold replication of hardware. However, processing is slower and latency in terms of clock cycles is longer than for parallel processing

To obtain favorable trade offs between speed of processing and digital hardware requirements, the W-bit words can each be divided into W/n subwords or digits of n bits each, providing W is a multiple of n. Then, the digits are serially subjected to parallel processing in n parallel bit streams.

M.J. Irwin and R.M Owens describe a specific system of this general sort in "Digit-Pipelined Arithmetic as Illustrated by the Paste-Up System: A Tutorial", Computer, Apr. 1987, pages 73-85. Irwin and Owen espouse a system wherein successive digits of a word are supplied in order of decreasing significance of their bits. Irwin and Owen in FIG. 3 of their article show a pipelined adder for such a system That adder requires two single-bit addition steps per bit of each digit Irwin and Owen avoid the need to wait for a carry that ripples up from the least significant end by using signed-digit or redundant arithmetic.

Such arithmetic is described by A. Avizienis in Signed-Digit Number Representations for Fast Parallel Arithmetic", IRE Transactions in Electronic Computers, Sept. 1961, pages 389-400. Signed-digit arithmetic is redundant in that positive and negative digits are differently represented Essentially, signed arithmetic costs a sign bit per digit, rather than just one sign bit per word. A pipelined arithmetic that is efficient is desirable, however, since a digital hardware saving of almost one-n^(th) would then be possible

If Irwin and Owen are correct in their opinion that most-significant-digit-first processing mandates redundant arithmetic, then least-significant-digit-first processing must be employed in order to use efficient digits.

S.G. Smith and P.A. Denyer describe the use of an efficient digital arithmetic with two-bit digits in "Radix-4 Modules for Higher-Performance Bit-Serial Computation", IEE Proceedings, Vol 134, Pt. E, No. 6, Nov. 1987, pages 271-276. They denominate normal bit-serial data communication carried out on a single wire as being "radix-two" bit-serial data communication. In radix-two-bit-serial communication, they note, computational elements have one logical input per input operand. An W-bit data word is transmitted least significant bit first and is processed in W clock cycles, one bit per clock cycle Smith and Denyer propose what they term "radix-four bit-serial" data communication which is performed concurrently on a pair of wires, one carrying even-numbered bits, the other odd-numbered bits. The concurrent bit pairs, or radix-four digits, represent side-by-side bit places from the data word; and data are transmitted in order of increasing bit significance. That is, the relatively less significant digits of a word are transmitted before the relatively more significant bits of a word Computational elements for the radix-four digital data have two logical inputs per input operand; and a W-bit, (W/2)-digit data word is processed in W/2 clock cycles Radix-four bit-serial data communication is also described in less particular terms in an earlier-published S G Smith, M.S McGregor and P.B Denyer paper "Techniques to Increase the Computational Throughout of Bit-Serial Architectures", IEEE Proceedings of ICASSP 1987, Apr. 1987, pages 543-546.

U.S. Pat. application Ser. No. 182,602, filed 18 Apr. 1988 by P.F. Corbett and R.I. Hartley issued 21 Aug. 1990 as U.S. Pat. No 4,951,221, entitled A CELL STACK FOR VARIABLE DIGIT WIDTH SERIAL ARCHITECTURE, assigned to General Electric Company and not acknowledged by this disclosure to constitute prior art adversely affecting the patentability of the present invention, is of interest. This application defines "digit-serial arithmetic" wherein W-bit operand words are grouped on the basis of bit significance into W/n successive digits of n bits each, which digits occur in successive clock intervals in order of increasing significance with passage of time. The n parallel bit streams that provide serial digit flow are accompanied by a control signal identifying the partitioning between successive words. U.S. Pat. No. 4,951,221 indicates that digit-serial data processing using digits of four to eight bits usually provides the best trade-offs between throughput rate and efficient utilization of monolithic-integrated-circuit die area. That is, radix-16, radix-32, radix-64, radix-128, or radix-256 digits are indicated to be generally preferable to radix-four digits. U.S. Pat. No. 4,952,221 notes that these optima had not been previously appreciated in the serial computational arts.

Of particular interest in the above-referred-to Nov. 1987 Smith and Denyer paper, insofar as the invention herein described is concerned, is the radix-four cascade adder of FIG. 6b in that paper. This adder is similar to cascade adders for digit-serial numbers for higher radix digits, as described in U.S. Pat. No. 4,951,221.

SUMMARY OF THE INVENTION

The invention is embodied in linear combining apparatus for combining first and second digit-serial operands, the words of which have W bits apiece supplied n bits at a time on W/n successive digits during respective clock intervals, n and W/n being plural integers. Generally it is preferable that n be at least three. The n bits of each digit of the first and second operands are identified by respective consecutive ordinal numbers first through n^(th) assigned in order of increasing significance. The linear combining apparatus includes a plurality in number of n full adders respectively identified by consecutive ordinal numbers first through n^(th), each full adder adding a bit of said first operand identified by the same ordinal number as it is either to the bit of said second operand also identified by the same ordinal number or to the complement of that bit. The carry bits generated by each of the first through (n-1)^(th) full adders is applied as carry input signal to the full adder with next higher ordinal number. Either the carry bit of the n^(th) full adder, as delayed by one clock interval, or a forced carry bit is selectively supplied as the carry input signal of the first full adder.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating the layout for a basic cell stack template that a silicon compiler may use in the generation of a mask-set for a monolithic integrated-circuit digital-serial linear combining circuit embodying the invention.

FIG. 2 is a block diagram illustrating a digit-serial adder having a digit width of four bits, which adder is described in U.S. Pat. application Ser. No. 182,602.

FIG. 3 is a block diagram illustrating an array of cell stacks arrayed in a row, at least one of which is a digit-serial linear combining circuit embodying the invention.

FIG. 4 is a schematic diagram of digit-serial linear combining apparatus having a digit width of four bits, which linear apparatus is an embodiment of the invention and provides subtraction capability as well as addition capability.

FIG. 5 is a schematic diagram of digit-serial linear combining apparatus which is an embodiment of the invention and provides comparison capability as well both addition and subtraction capabilities.

FIG. 6 is a table useful in understanding of how comparison is done in the FIG. 5 apparatus.

Each of FIGS. 7 and 8 is a schematic diagram of a respective linear combining apparatus, which is alternative to that of FIG. 5 and embodies the invention.

FIG. 9 is a block diagram that shows how two linearing combining apparatuses per FIGS. 2, 4, 5, 7 or 8 can be connected to provide double-precision addition.

FIG. 10 is a schematic diagram of an adder array through which there are systolic signal flows and in which digit-serial processing is employed, which adder array embodies the invention.

FIG. 11 is a schematic diagram of another adder array through which there are systolic signal flows and in which digit serial processing is employed, which adder array also embodies the invention.

FIG. 12 is a schematic diagram that shows details of a parallel-to-digit-serial converter as used sevenfold in each of the FIG. 10 and FIG. 11 adder arrays.

FIG. 13 is a schematic layout diagram that shows details of a bit-slice cell for linear combining apparatus embodying the invention.

FIG. 14 is a schematic layout diagram that shows details of a control cell for linear combining apparatus embodying the invention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 illustrates, in block diagram form, a cell stack structure convention used by a silicon compiler that is used to generate mask-set for monolithic integrated-circuit digit-serial circuits such as digit-serial linear combining circuits embodying the invention. Cell stack 10 includes a cap cell 12 disposed at the top of a vertical stack of cells. At the bottom of the vertical stack there is a control cell 14. Between cap cell 12 and control cell 14 there are disposed a plurality n, of operation cells 16. The number of operation cells, n, corresponds to the number of bits in the selected digit size Each of the operation cells 16 is operable to carry out one or more single-bit operations. Cap cell 12, operation cells 16 and control cell 14 are arranged in a vertical stack in which each cell is approximately the same width. Cap cell 12 is employed to carry the V_(SS) power bus and may be used to make minor routing connections Control cell 14 carries the V_(DD) power bus. These power busses are typically the different polarity power conductors from an operating supply power connection which is made to the chip on which cell stack 10 is incorporated. The cap cell 12 and the control cell 14 are preferably configured to provide continuous conductive paths connecting adjacently disposed cell stacks so that adjacently disposed cell stacks each are connected to the desired power supply conductors Control cell 14 typically includes circuitry for carrying out tasks such as delaying and resetting carry signals, buffering and inverting clock signals, and performing any other necessary logic control. The function of each control cell 14 generally varies from cell stack to cell stack, presuming the functions of those cell stacks to differ.

For all cell stacks which conform to the basic template shown in FIG. 1, the height of these stacks is constant. Thus, if G and H are two such cell stacks, the control cell for stacks G and H are equal in height. Similarly, the bit slices (operation cell areas) of stacks G and H are equal in height, as are the cap cells. The width of the cell stacks may be different for cell stacks performing different functions. As a result of this standardization of structure, the total cell stack height of all n-bit digit serial operators is the same. The height of a cell stack is given by the following formula:

    total-height=cap-height+control-height +(n×slice-height) (1)

total-height =cap-height +control-height

Furthermore, power and clock signals, preferably being at standard locations in the control and cap cells, provide matched connections between adjacently disposed cell stacks. Because of this, cell stacks may be placed side by side in rows of cell stacks of equal height. However, it is also possible to provide a small separation or "routing channel" between adjacently disposed cell stacks over which connections may be routed. This is desirable so that cells may be placed and connections between them routed with efficient standard cell place-and-route methods.

While FIG. 1 shows cap cells disposed at the top of a vertical stack and control cells disposed at the bottom of this same stack, it is noted that this is not the only possible arrangement of these three different types of cells within a stack. However, it is the preferred embodiment It is, however, noted that it would be readily possible to interchange the placement of the control cells and cap cells without significantly affecting the practice of the present invention. Similar objectives could also be obtained simply by disposing the stack cells shown in FIG. 1 in an inverted position However, in this case, the general signal flow path from one side of the stack to the other is reversed In fact, this reversal may provide advantages in overall chip layout in which an overall signal flowpath is provided on a chip in a zigzag fashion. The silicon compiler can also pervert cells in its library to provide reversal of signal flow without inverting the stack 10 of cells.

FIG. 2 schematic diagram shows a 4-bit digit-serial adder as described in application serial number 182,602. This adder is of a type that can be configured, as shown, in a stack 100 that conforms to the conventional cell stack 10 arrangement of FIG. 1. Cap cell 120 contains a V_(SS) power bus 22 which is configured to readily connect adjacent cell stacks and also to provide a first operating supply voltage V_(SS) to operation cells 160 and to control cell 140. Likewise, cap cell 120 includes clock line 26 which again is readily connectable to adjacent cells and is operable to supply clock timing signals to each of operation cells 160. Control cell 140 includes a V_(DD) power bus conductor 24 which is likewise readily connectable to adjacent cell stacks. Power bus 24 also supplies to operation cells 160 a second operating supply voltage V_(DD) differing by a few volts from the first operating supply voltage V_(SS).

In the particular embodiment shown, a 4-bit digit-serial adder is described, but the cell stack may be modified to include fewer or more operation cells 160 to accommodate other widths of digit in terms of bits. Each operation cell 160 includes full adder 28 receiving digit-serial inputs A_(i) and B_(i). Here, i ranges from 0 to 3, reflective of the four bits in each digit. (For convenience, the input ports of the full adders 28 which receive the digit-serial input bits A_(i) may be denominated "augend" input ports, and the input ports of the full adders 28 which receive the digit serial input bits B_(i) may be denominated "addend" input ports. It should be understood, however, that the addition operation in a full adder 28 is unaffected by whether ah A_(i) term is added to a B_(i) term, or vice versa.) The sum output signal of each full adder 28 is supplied to a respective unit-clock-delay block 32, the output ports of which provide digit-serial output data via lines labeled XOUT₀ through XOUT₃, as shown. The carry-out signal from each of the full adders 28, except that in the last operation cell #4 is supplied as carry-in signal to the full adder 28 in the operation cell with next higher number. Each operation cell 160 is the same. Each operation cell 160 individually performs a single-bit operation; however, collectively these cells perform a 4-bit digit-serial addition operation.

The digit-serial adder shown in FIG. 2 also includes control cell 140 particularly configured to control the flow of carry information (at the digit level). In particular, it is seen that control cell 140 receives control signal information which is inverted by inverter 38 and supplied to AND gate 36, which gate 36 also receives high-order digit carry information from the full adder 28 in the last operation cell #4. In operation, the control cell 140 selects either a ZERO as forced carry bit or the carry-out signal from the full adder 28 processing most significant bits of the digit; delays the selected bit one cycle by passage through a unit-clock-delay block 34 and supplies the delayed bit the next clock cycle, as carry-in signal to the full adder 28 in the first operation in cell #1. Control cell 140 selects the ZERO as forced carry bit in a reset operation. This reset operation is shown in FIG. 2 as being controlled by the control signal line labeled CONTROLMSD in FIG. 2 which is high (ONE) only in the last, most significant digit of each data word. The forced carry reaches the full adder 28 in the first operation cell #1 input signals during the first digit of the next word.

In general, data words are divided into a plurality of digits, each of size n. For example, if the word size is W and the digit size is n, there will, in general, be W/n passages of information through the adder cell stack to effect the addition of two words of W bits each. Where the number n of bits per digit is only three, cell stack 100 is modified to omit operation cell #4, the carry output signal from the full adder 28 in cell #3 is applied to AND gate 36 in control cell 140, and provision is made for continuing to apply the carry output signal from delay block 34 to line 21. Where the number n of bits per digit is greater than n by some integer m, cell stack 100 is modified by inserting in additional operation cells 160 into the stack.

In an alternative adder embodying the invention, delay block 34 could be relocated to the input connection of AND gate 36 from the last full adder 28, and the control signal received via inverter 38 would be a CONTROLLSD signal that would be high (ONE) only during the first, least significant digit of each data word. It is also noted that while carry signal line 21 is shown in FIG. 2 as being completely disposed in the cell stack 100, alternatively line 21 can be routed over a routing channel 42 between adjacently disposed cell stacks, as will be discussed in greater detail further on in connection with FIG. 3.

In FIG. 2, input data signals are supplied from the left, and output data signals are taken from the righthand side of the cell stack 100. However, it is noted that operation cells 160 may be laid out in reverse fashion, with data signals being directed to the left. In fact, it may be desirable to employ both kinds of cell stacks on the same chip. That is to say, on a given chip employing the present invention, data signals are not limited to flowing from either the left to the right or from the right to the left in a given cell stack. However, consistency in flow direction is generally advisable between adjacently disposed and electrically connected cell stacks.

FIG. 3 illustrates a cell stack array 40 assembled from a plurality of cell stacks 10, one or more of which may be a digit-serial adder of the sort shown in FIGS. 2, 4, 5 or 6 or their like. In particular, different cell stacks 10 from a relatively small library of cell stack operators can be seen to be readily configured in adjacent locations It is seen that power busses 22 and 24 are readily connected between adjacent cell stacks 10. The same is true for the clock signal 26. Furthermore, clock signal line 26 is shown as being present in cap cell 12. It is also possible to dispose a clock signal line in control cell 14, as well, or instead.

A particular advantage of the general cell stack configuration depicted in FIG. 1 is that the cell library does not have to contain and maintain a large number of different cell stack operators for different digit sizes. The digit size is entirely controllable simply by changing the stack height and by including the appropriate number of bit-slice operation cells 16. Extremely flexible design is facilitated without sacrificing layout efficiency.

Cell stacks 10 shown in array 40 of FIG. 3 may actually comprise different kinds of digit-serial operators. Accordingly, the cell stacks are typically of varying widths even though a constant width is illustrated in FIG. 3. Nonetheless, the cell stack height is substantially constant for given bit-width digits. In those signal processing applications in which data may be passed directly from one operator stack to the next, it is possible to dispose the cell stacks in substantially abutting relationships. However, in those situations in which it is desirable to re-route signal or control signal lines between cell stacks, it is desirable to employ routing channel 42 which is disposed between adjacent cell stacks. For example, signal line 21 shown in FIG. 2 may in fact be disposed in one of these routing channels rather than being disposed within the operation cells. In this case, it is a matter of design choice which of the two locations for signal line 21 is selected.

A FIG. 3 cell stack array wherein each cell stack is a digit-serial adder per FIG. 2, or its like, may be used for chain addition wherein an auguend is successively incremented with a plurality of addenda, with each successive addendum being added by a respective cell stack 10, that is configured like cell stack 100 Each successive addendum is subjected to one more unit clock delay than its predecessor to compensate for the latency of the preceding cell stack 100. In such arrangement, the partial sum signal generated by the respective digit serial adder in each of these cell stacks 10 (or 100) crosses the routing channel 42 at the right of that cell stack 10 to supply the auguend for the cell stack 10 (or 100) at its left. Each of the respective addenda for the cell stacks, except perhaps the addendum for the cell stack at extreme left, is directed down signal lines running down the routing channel 42 at the left of that cell stack 10.

A FIG. 3 cell stack array can also be configured to perform chain addition or subtraction using linear combining apparatuses per FIGS. 4, 5 or 6 as will become apparent after reading the descriptions of those figures occurring further on in this application. Chain additions or subtractions can, of course, be performed on a tree rather than a cascade basis to reduce latency time for obtaining final result; this will complicate routing of interconnections somewhat, but will save some unit delay blocks.

This specification will describe the use of exclusive-OR or XOR gates, and it will describe the use of exclusive-NOR gates. Since some of these gates will have more than the two input signals normally encountered in practice, the definition of those gates is now reviewed. An exclusive-OR gate is a logic device that generates an output signal that is a ONE responsive to each of only an odd number of its input signals being a ONE and each other of its input signals being a ZERO, and otherwise generates an output signal that is a ZERO. An exclusive-NOR gate is a logic device that generates an output signal that is a ZERO responsive to each of only an odd number of its input signals being a ONE and each other of its input signals being a ZERO, and otherwise generates an output signal that is a ONE.

FIG. 4 shows a cell stack 101 that operates a digit-serial adder/subtractor. That is, cell stack 101 provides a digit-serial linear combining apparatus that can perform signed additions, both positive additions and negative additions or subtractions. Cell stack 101 can be operated as an adder or as a subtractor depending on signals applied to its control cell 141. The operation cells 161 of cell stack 101 differ from operation cells 160 of cellstack 100 of the digit-serial adder in that exclusive-OR gates 44 are included as shown in FIG. 4 to perform (on a selective basis) bit complementation of the B_(i) signals as they are applied to full adders 28. Each B_(i) input signal (where i is the operation cell number less one) is supplied as one input of an XOR gate 44, the other input of which connects to a bus 46 shared by all the operation cells 161. Bus 46 is receptive of a MODE command, which is a ZERO when addition is being done and is a ONE when subtraction is being done by the FIG. 4 adder/subtractor. During addition, responsive to the ZERO applied to bus 46, the XOR gates 44 respond to the B_(i) bit signals to repeat them for application to full adders 28. During subtraction, responsive to the ONE applied to bus 46, the XOR gates 44 respond to the B_(i) bit signals with their bit complements for application to full adders 28.

Again, for convenience, the input ports of the full adders 28 receptive of A_(i) bits may be denominated "augend" input ports, but they may alternatively be denominated "minuend" or "augend/minuend" input ports in recognition of the role they take during subtraction. Similarly the input ports receptive of Bi bits may be denominated "addend" input ports, but they may alternatively be denominated "subtrahend" or "addend/subtrahend" input ports.

When doing subtraction, the carry input supplied at the beginning of such subtraction to the full adder 28 of operation cell #1 via line 21 must be a ONE, rather than the ZERO supplied at the beginning of each addition. The initial carry bit be it a ONE or ZERO is applied to the CARRYING input of control cell 141 for application to a multiplexer 48, which selects this signal to line 21 during the initial least significant digits of the arithmetic words A and B being linearly combined. This selection is made responsive to the CONTROLLSD command supplied on CONTROLLSD input to control cell 141 during these initial digits of the arithmetic words A and B being a ONE. During the later digits when the CONTROLLSD signal is a ZERO, multiplexer 48 selects the carry output of the full adder 28 in the last operation cell #4 as delayed by delay block 34 for application to line 21.

The reason for placing multiplexer 48 after delay block 34 and controlling it with CONTROLLSD rather than CONTROLMSD signal is that CARRYING signal is then temporally aligned with MODE signal for the case where the linear combining apparatus is called upon to intermix positive additions and negative additions or subtractions. When MODE signal is a ONE during subtraction that same ONE can be applied as CARRYING signal, eliminating the need to forecast the MODE signal in order to ascertain the CARRYIN signal. The reason for keeping the MODE and CARRYIN signals separate, however, is to implement dual-or multiple-precision additions or subtractions. Dual-precision addition or subtraction will be discussed further on, in connection with FIG. 9 of the drawing.

The FIG. 5 linear combining apparatus is not only an adder/subtractor, but also provides for comparing operand B with operand A to determine if operand B is at least as positive (or large) as operand A or if it is more negative (or smaller) than operand A. Theoretically such comparison can be made by subtracting operand B from operand A and noting the sign of the resulting difference. When the possibility exists that the subtraction will cause overflow in the difference, however, the sign bit of the difference may provide "erroneous" comparison result.

Consider, for example, the subtraction of a B operand of minus four, from an A operand of plus five, assuming a word of four bits. Four-bit two's complement numbers have a range from minus eight to plus seven, and the plus nine result of subtracting minus four from plus five will overflow this range. The normal subtraction procedure for two's complement numbers is to perform bit complementation on the subtrahend before adding it to the minuend as augmented by a number consisting of all ZEROs except for a ONE in the least significant bit place. Complementing the bits 1100 of minus four provides a number 0011 to be added to plus five, 0101, and to 0001. The result of adding 0011, 0101, and 0001 is 1001 or minus seven, an "error" caused by the wrap around of plus nine overflow into the bottom of the negative number field. The sign bit of minus seven is a ONE, rather than a ZERO, which incorrectly indicates operand B to be at least as positive as operand A.

The correct sign of the result of an addition or subtraction process can be determined without error, dependent not only in the sign bit of the result, but also dependent on the value of the overflow or carryout bit C_(MSB) from the full adder for sign bits. The difference (A-B) is greater than or equal to zero if and only if C_(MSB) is a ONE, providing A and B are alike in sign and CARRYIN is a ONE The difference (A-B) is greater than or equal to zero if and only if C_(MSB) is a ZERO, providing A and B differ in sign and CARRYIN is a ONE. The difference (A-B) is less than or equal to zero if and only if C_(MSB) is a ZERO, providing A and B are alike in sign and CARRYIN is a ZERO. The difference (A-B) is less than or equal to zero if and only if C_(MSB) is a ONE, providing A and B differ in sign and CARRYIN is a ZERO.

FIG. 6 is a table that provides an aid for understanding why these postulated rules are so when arithmetic words have four bits. The reader after reading the following explanation of the FIG. 6 aid should be able to develop or to imagine more extensive tables as aids for understanding why these postulated rules are so for words having other numbers of bits.

Column A at left of FIG. 6 table lists from bottom to top the ascending values of operand A from minus eight to plus seven in two's complement binary numbers. The column next to the right, but left of the middle of the table, lists in the same row as each operand A value in column A that two's complement binary number which when added to that operand A value would be just sufficient to cause carry-out overflow--i.e., to make C_(MSB) a ONE.

Subtraction of operand B from operand A is implemented in two's complement binary numbers by adding to A the one's (or bit) complement of B and to an input carry bit of a least-significant-bit ONE. (The input carry may be thought of as a number with ZEROs in all bit places except the ONE in the least-significant bit place). Column B at right of FIG. 6 table lists in the same row as each value of operand A in column A that value of operand B that would have to be one's complemented and augmented by input carry of ONE to generate the value in the same row in the column just to the right of column A. The column just to left of column B lists in each row thereof the one's (or bit) complement of the value of operand B in the same row in column B, to help in understanding the steps of the procedure used during subtraction to progress from column B to the second column to the left of column B.

There are now only four general cases of how operands A and B compare to each other to be considered in order to validate the rules previously postulated with regard to how the carry-out overflow bit C_(MSB) can be used to determine the results of comparing operands A and B. In considering these four general cases, the sign bit of the A operand will be designated S_(A) and the sign bit of the B operand will be designated S_(B). S_(A) and S_(B) are the most significant bits of the two's complement operands A and B, respectively.

The first case to be considered is when A and are both positive - i.e., S_(A) and S_(B) are both ZEROs. Referring to FIG. 6 table, one notes if operand B is in a row lower than that of operand A - i.e., A>B or (A-B)>0- the one's complement of operand B even as not augmented by input carry of ONE is large enough to cause C_(MSB) to be a ONE. If operand B is in a row higher than. that of operand A - i.e., A B or (A-B)<0--the one's complement of operand B even as augmented by input carry of ONE is not large enough to cause C_(MSB) to be a ONE, so C_(MSB) is a ZERO. If operands A and B are in the same row--i.e., A=B or (A--B)=0 --C_(MSB) will be ONE if input carry of ONE is applied and will be ZERO if it is not. So, (A-B)≧0, if and only if C_(MSB) is ONE, and (A-B)<0 if and only if C_(MSB) is ZERO, both providing input carry of ONE is applied. Alternatively, (A-B)>0, if and only if C.sub. MSB is ONE, and (A-B)≦0 if and only if C_(MSB) is ZERO, both providing input carry of ZERO is applied.

The second case to be considered is when A and B are both negative - i.e., S_(A) and S_(B) are both ONEs. Referring to FIG. 6 table, one notes if operand B is in a row lower than that of operand A--i.e., A<B or (A-B)>0 - the one's complement of operand B even as not augmented by input carry of ONE is large enough cause C_(MSB) to be a ONE. If operand B is in a row higher than that of operand A--i.e., A B or (A-B) 0 --the one's complement of operand B even as augmented by input carry of ONE is not large enough to cause C_(MSB) to be a ONE so C_(MSB) is a ZERO. If operands A and B are in the same row--i.e., A=B or (A-B)=0-C_(MSB) will be ONE if input carry of ONE is applied and will be ZERO if it is not. So, (A-B)≧0, if and only if C_(MSB) is ONE, and (A-B)<0, if and only if C_(MSB) is ZERO, both providing input carry of ONE is applied. Alternatively, (A-B)>0, if and only if C_(MSB) is ONE, and (A-B)≦0 if and only if C_(MSB) is ZERO, both providing input carry of ZERO is applied Comparing the observations made concerning the first and second cases, they are the same.

The third case to be considered is when A is positive and B is negative - i.e., S_(A) is a ZERO and S_(B) is a ONE. In such case (A-B) will invariably exceed zero. Referring to FIG. 6 table, one notes that even the largest positive A operand 0111 when added to the largest complement 1111 of B operand, whether or not augmented by a CARRYIN of ONE (0001), does not result in overflow to cause C_(MSB) to be a ONE. If a ONE indication of A-B≧0 is required, C_(MSB) must be one's complemented.

The fourth case to be considered is when A is negative and B is positive - i.e., S_(A) is a ONE and S_(B) is a ZERO In such case (A-B) will invariably be smaller than zero. Referring to the FIG. 6 table, one notes that even the smallest binary number 1000 as negative A operand when added to even the smallest complement 1000 of a positive B operand, whether or not augmented by a CARRYIN of ONE (0001), invariably results in overflow to cause C_(MSB) to be a ONE. If a ZERO indication of A-B≧0 is required, C_(MSB) must be one's complemented.

Whether one of the first and second cases obtains, or whether one of the third and fourth cases obtains can be distinguished, either by applying S_(A) and S_(B) to an exclusive-OR gate to obtain its response, or by applying S_(A) and S_(B) to an exclusive-NOR gate. The C_(MSB) can then be selectively complemented, not to be complemented when one of the first and second cases obtains, and to be complemented when one of the third and fourth cases obtains.

FIG. 5 shows each operation cell 162 in cell stack 102 including an exclusive-NOR gate 50. The exclusive-NOR gate 50 in the last operation cell (#4) the full adder 28 of which cell supplies C_(MSB) as its carry output receives A₃ which during the last digit of the digit serial operand A₃ corresponds to S_(A). That exclusive-NOR gate 50 also receives from exclusive-OR gate 44 the one's complement of B_(3;) B₃ during the last digit of the digit serial operand B corresponds to S_(B), so the one's complement of B₃ corresponds to S_(B) that digit The logic response of exclusive-NOR gate 50 in operation cell #4 is the logic complement of S_(A) ⊕S_(B), where the circled plus sign signifies the exclusive-OR operation. The logic complement of S_(A) ⊕S_(B) can be be shown by comparison of truth tables to be equal to S_(A) ⊕S_(B). Exclusive-NOR gate 50 in operation cell #4 supplies a ZERO when the first or second case of S_(A) or S_(B) conditions obtains and a ONE when the third or fourth case obtains.

An exclusive-OR gate 52 in a control cell 142 of cell stack 102 selectively complements C_(MSB) from full adder 28 in the last operation cell (#4) in accordance with the output signal from exclusive-NOR gate 50 in that operation cell. The S_(A) ⊕S.sub. ⊕B C_(MSB) response of XOR gate 52, when MODE signal is a ONE, appears during the last digits of operands A and B, and this response is latched by latch 54 at that time responsive to a CONTROLMSD input signal to control cell 142. Latch 54 maintains the comparator output signal COMPOUT so latched until the next time last digits of operands A and B appear in the pipeline. When MODE signal is a ZERO, latch 54 latches S_(A) ⊕S_(B) ⊕S_(C) or S_(a) ⊕S_(B) ⊕S_(C) / response instead until the next time last digits of operands A and B appear in the pipeline.

Control cell 142 like control cell 141 of FIG. 4 includes a multiplexer 48 and a delay block 34, and the connections of these elements is similar. The CONTROLLSD signal for controlling the operation of multiplexer 48 is obtained, however, by delaying CONTROLMSD for one digit interval using a unit-clock-delay block 56.

FIG. 7 shows an adder subtractor/adder/comparator alternative to that shown in FIG. 5. The cell stack 103 of the FIG. 7 linear combining apparatus uses simpler operation cells 163 in which exclusive-NOR gates 50 do not appear. A control cell 143 similar to control cell 142 of FIG. 4 except for two-input exclusive-OR gate 52 being replaced by a three-input exclusive-NOR gate 58 is included in cell stack 103. Exclusive-NOR gate 58 receives A₃, B₃ as selectively complemented by XOR gate 44 in operation cell #4, and C_(MSB) as its three input signals. By comparison of truth tables three-input exclusive-NOR gates can be shown to be the logic equivalent of two-input exclusive-0R gate 52 and the particular two-input exclusive-NOR gate 50 that supplies its output response to exclusive-OR gate 52.

FIG. 8 shows another approach to the simplification of the FIG. 5 digital hardware. In the FIG. 8 adder/subtractor/comparator the same control cell 142 is used as in FIG. 5. Hardware reduction is achieved in each of the operation cells 164 included in a cell stack 104 with the control cell 42. This reduction comes about by recognizing that a three-input exclusive-NOR gate 60, which is the equivalent of two-input exclusive-OR gate 44 and two-input exclusive-NOR gate 50, can be utilized to provide a substantial portion of a full adder. A two-input exclusive-NOR gate 62 in cascade with exclusive-NOR gate 60, if MODE signal be ZERO, provides the equivalent logic response A_(i) ⊕B_(i) ⊕C_(i) of the cascade of two XOR gates, one to XOR the input operands, and one to XOR the result with CARRYIN, that are used in the canonic full adder configuration to generate the sum bit output signal C_(i) is the CARRYIN bit to the #i operation cell 164, where i =0, 1, 2, 3.

If MODE signal be ZERO, the carry out bit of a full adder is well known to be a ONE if at least two of A_(i), B_(i) and C_(i) are ONEs. If A3 and B3 are both ZEROs exclusive-NOR gate 60 output is a ONE so multiplexer 64 in operation cell #4 selects A₃, a ZERO, as its carry out. If only one of A₃ and B₃ is a ONE, exclusive-NOR gate 60 output is a ZERO, so multiplexer 64 in operation cell #4 selects carry in as carry out. Carry out bit is only ONE if carry in bit is a ONE so two of A_(i), B_(i) and C_(i) are ONEs. If both A₃ and B₃ are ONEs, exclusive-NOR gate 60 output is a ZERO, so multiplexer 64 in operation cell #4 selects A₃, a ONE, as its carry out. Note it is immaterial whether A₃ or B₃ connects to the input port of multiplexer 64 selected by exclusive-NOR gate 60 output bit being a ZERO.

In these analyses, MODE signal has been assumed to be ZERO, so exclusive-NOR gates 60 operate as two-input gates for A_(i) and Bi. The three-input exclusive-NOR gates 60 are the equivalent logically of an exclusive-OR gate for B_(i) and MODE supplying input to a two-input exclusive-NOR gate for (B_(i) ⊕MODE) and for A_(i), it will be appreciated that full adder operation after selective inversion of B_(i) obtains, whether or not MODE signal be a ONE or a ZERO.

FIG. 9 shows how dual-precision additions may be done with two linear combining apparatuses per FIG. 4, 5, 7 or 8. The need for dual-precision additions arises, for example, in linearly combining the dual-precision products of two digit-serial multiplier apparatuses (not shown in FIG. 9). In such digit-serial multiplier apparatuses the minor product word, comprising the less significant digits of the full product, completes its arrival in successive digits through a first n-bit-wide pipeline before the major product, comprising the more significant digits of the full product, begins its arrival in successive digits through a second n-bit-wide pipeline.

In FIG. 9 the digit a_(o) followed by digit a₁, both followed by digit a₂, all followed by digit a₃, together constitute the minor product of a first multiplier apparatus applied as operand A to a linear combiner 66. The digit b_(o) followed by digit b_(l), both followed by digit b₂, all followed by digit b₃, together constitute the minor product of a second multiplier apparatus applied as operand B to linear combiner 66. Linear combiner 66 receives a MODE signal that is a ZERO, conditioning it to function as an adder, and accordingly its CARRYIN signal is also made a ZERO. The CARRYOUT signal from linear combiner 66 is supplied as CARRYIN signal to a further linear combiner 68.

The digit a₄ followed by digit a₅, both followed by digit a₆, all followed by digit a₇, together constitute the major product of the first multiplier apparatus and are applied as operand A to the linear combiner 68. The digit b₄ followed by digit b₅, both followed by digit b₆, all followed by digit b₇, together constitute the major product of the second multiplier apparatus and are applied as operand B to the linear combiner 68. Linear combiner 68 receives a MODE signal that is a ZERO, conditioning linear combiner 68 to function as an adder, and accordingly its CARRYIN signal is also made a ZERO.

The dual-precision digital sum of the first and second multiplier products appears on two n-bit-wide busses 70 and 72. The initial digits x_(o), x₁, x₂ and x₃ appear sequentially on bus 70 being supplied from linear combining apparatus 66. Thereafter final digits x₄, x₅, x₆ and x₇ appear sequentially on bus 72 being supplied from linear combining apparatus 68.

The FIG. 9 circuitry may be modified to subtract the digit-serial dual-precision products b_(o), b₁, b₂, b₃, b₄, b₅, b₆, b₇ of the second multiplier from the digit-serial dual-precision product a_(o), a₁, a₂, a₃, a₄, a₅, a₆, a₇ of the first multiplier. This modification entails the MODE signals applied to linear combining apparatuses 66 and 68 both being ONEs and the CARRYIN signal supplied to linear combining apparatus 66 being a ONE as well. Similarly, plural-precision comparison can be performed using the same connection as for plural-precision comparison, or modifying those connections by applying a ZERO as CARRYIN signal to linear combining apparatus 66. The FIG. 9 linear combining circuitry may be adapted to perform linear combination on a multiple-precision rather than dual-precision basis using one or more further cell stacks 101, 102, 103 or 104 to supplement cell stacks 66, 68, with the CARRYIN of each supplemental cell stack being supplied by the cell stack handling the next less significant group of digits.

FIG. 10 shows an adder array through which there are systolic signal flows. In the FIG. 10 adder array, parallel-bit signals A, B, C, D, E, F, G and H are converted to digit serial form in parallel-to-digit-serial converters 75, 76, 77, 78, 79., 80, 81 and 82, respectively, and are then added together in a tree of digit-serial adders 93-99. The tree of digit-serial adders 93-99 generates the sum A+B +C+D+E+F+G+H in digit-serial format. As will be described more particularly further on with reference to FIG. 12, each parallel-to-digit-serial converter includes a plurality of parallel-in/serial-out registers, which registers are essentially side-loaded shift registers clocked in two phases during shifting of parallelly-loaded data to supply serial bit streams that together provide digit-serial data to the tree of digit adders 93-99. A clock generator 200 generates the two phases C1 and C2 of clock signal and their logic co C1B and C2B that applied to the parallel-to-digit-ser (which application is for the sake of clarity specifically shown in FIG. 10). The two phases Cl and are shown being generated in complementary form since the shifter stages in converters 75-82 are presumed to be constructed using complementary metal-oxide-semiconductor (CMOS) field-effect transistors. A counter 301 is used as a pulse frequency divider with its full count equallying the number of digits per digit-serial word. A decoder 202 decodes the full count condition to reset the counter 201 to zero count and to apply a LOAD command distributed to each of the parallel-to-digit-serial converters 75-82 Adders 93-99 are assumed to be of one of the types shown in FIGS. 2, 5 and 8, each of which requires the application of CONTROL MSD indications. The output signal from the decoder 201 also supplies the most-significant-digit CONTROL MSD indication signal to the first rank of digit-serial adders (93-96) of the adder tree. A unit-clock-delay block 203 generates a CONTROL MSD indication signal for the second rank of digit-serial adders (97, 98) to the CONTROL MSD indication signal for the first rank of digit-serial adders (93-96). A unit-clock-delay block 204 generates a CONTROL MSD indication signal for the third rank of digit-serial adders (99). The digit-serial sum output signal from the digit-serial adder 99 in this third and last adder rank is shown as being converted to parallel-bit form by a digit-serial-to-parallel converter 205. Converter 205 may, by way of example, be of the form shown in FIG. 11 of U.S. Pat. No. 4,942,396 issued 17 July 1990 to R.I. Hartley et al. and entitled "TO-DIGIT-SERIAL CONVERTERS FOR SYSTEMS PROCESSING DATA IN DIGIT-SERIAL FORMAT".

FIG. 11 shows an adder array similar to that in FIG. 10, but in which the CONTROL MSD indication signals for the second rank of adders (97, 98) is generated by a decoder 206 decoding zero count from counter 201 and in which the CONTROL MSD signals for the third rank of adders (99) is generated by a decoder 207 decoding unity count from counter 201. Variations of the FIGS. 10 and 11 adder arrays using adders of the type shown in FIG. 4 will be apparent to one skilled in the art of digital design. In considering the nature of any one of the parallel-to-digit-serial converters 75-82 in connection with the following description of FIG. 12, the parallel-bit input signal A, B, C, D, E., F, G or H to the converter will be generally denominated as "Q".

FIG. 12 shows the nature of the parallel-to-digit-serial converter 84, supposing word length W is sixteen bits and digit width n is four bits. The sixteen bits of Q are segregated into four spatial phasings according to the bit position they will assume in the digit-serial format. Q₀, Q₄, Q₈ and Q₁₂ are loaded in parallel into a first parallel-in/serial-out register 86, responsive to a LOAD COMMAND signal, applied just prior to the least significant digit of the quotient being clocked out in digital serial format. Q₁, Q₅, Q₉ and Q₁₃ are, responsive to LOAD COMMAND signal, loaded in parallel into a second parallel-in/serial-out register 88 at the same time register 86 is loaded. Q₂, Q₆, Q₁₀ Q₁₄ are, responsive to LOAD COMMAND signal, loaded in parallel into a third parallel-in/serial out register 90 at the same time registers 86 and 88 are loaded. Q₃, Q₇, Q₁₁ and Q₁₅ are, responsive to LOAD COMMAND signal, loaded in parallel into a fourth parallel-in/serial-out register 92 at the same time registers 86, 88 and 90 are loaded. Parallel-in/serial-out registers 86, 88, 90 and 92 are sometimes referred to as "side-loaded shift registers" in the literature. After being parallelly loaded, registers 86, 88, 90 and 92 have their contents shifted out at digit clock rate to supply respective ones of the bit streams of the digit-serial quotient Q.

FIG. 13 is the actual stylized layout diagram supplied to integrated-circuit technicians who designed the mask set for operation cell 164 of FIG. 8, which cell 164 is identified as ASUBSLICE1 in FIG. 13. The layout diagrams of FIGS. 13 and 14 use control signals supplied in both complemented and non-complemented form because complementary-metal-oxide-semiconductor (CMOS) circuits, which are familiar to those skilled in the art, are utilized. Lines M and MB crossing operation cell 164 convey the MODE signal and its complement respectively. V_(SS) and V_(DD) operating voltage lines also cross the operation cell. Lines C0 and Cl convey the carry in and carry out bits to the operation cell. Lines A and B receive the A and B operands, respectively. Line CR is the carry return line 21 of FIG. 8 moved in position within the operation cell.

Multiplexers AS019 and AS020 and inverters AS011, AS014, AS015 and AS016 together provide an exclusive-OR gate for operand A supplied on line A, operand B supplied on line B, and MODE signal supplied in complementary forms on lines M and MB. An inverter AS009 complements the XOR gate response to appear on line EQ as an exclusive-NOR response to A, B and MODE signals; and a further inverter AS008 complements the exclusive-NOR response inverter to appear as exclusive-OR response on line NEQ.

A multiplexer AS021 corresponds to multiplexer 64 of FIG. 8 except for selecting between the complements of A operand and carry-in signals rather than the signals themselves A operand is complemented by an inverter AS017, and carry-in signal arriving on line C1 is complemented by an inverter AS013. Multiplexer AS021 response is inverted by an inverter AS010 thereafter, so either A or carry-in signal is applied to C0 line as carryout signal responsive to multiplexer AS021 selection.

A multiplexer AS022 selects, either the complement of carry input signal as supplied by inverter AS013, or the carry input signal developed by again complementating in a further inverter AS018, which selection is controlled by signals appearing in complemented form on lines EQ and NEQ. These connections cause multiplexer AS022 to function as XOR gate 62. AS012 is the clocked-unit delay latch 32 of FIG. 8. It receives first and second phases of clocking signal on lines Cl and C2, respectively; and their complements on lines C1B and C2B respectively.

FIG. 14 is the actual stylized layout diagram for a control cell ASUBCONT, corresponding substantially to control cell 142 as shown in FIG. 8 (or 5), as supplied to integrated circuit technicians. An inverter AS09 complements the signal received at MODE input connection to supply line MB running to the operation cells ASUBSLICEl, and a further inverter AS08 regenerates the MODE signal by complementing its complement to supply line M running to operation cells ASUBSLICE1.

Responsive to clock signal of a first phase supplied via CLOCK 1 bus, cascaded inverters AS04 and AS07 respectively generate the complement of that clock signal on line C1B and regenerate that clock signal on line Cl. Responsive to clock signal of a second phase supplied via CLOCK 2 bus, cascaded inverters AS05 and AS06 respectively generate the complement of that clock signal on line C2B and regenerate that clock signal on line C2. Lines C1, C1B, C2 and C2B connect to extensions of these lines in the ASUBSLICE1 operation cells in stack with ASUBCONT control cell.

The clock signals on lines Cl, C1B, C2 and C2B are utilized by the unit-clock-delay element AS01, corresponding to delay block 34 in FIG. 8, which element AS01 delays the carry-out signal from the last operation cell as supplied on the carry-in line C1 of ASUBCONT control cell. The clock signals on lines Cl, C1B, C2 and C2B are also utilized by the unit-clock-delay latch element AS02, corresponding to latch 54 of FIG. 8, which element AS02 supplies a latch output signal GELT that is either the equivalent of COMPOUT signal of FIG. 8 or its one's complement.

Connection CONTROL of ASUBCONT corresponds to connection CONTROLMSD of control cell 142. The CONTROL MSD signal applied thereto is complemented by an inverter AS19 to drive line CONTB and is then re-complemented by an inverter AS18 to drive line CONT The signals CONT and CONTB lines control the loading of latch element AS02, just as signal on CONTROL MSD line controls latch 54 in FIG. 8.

Inverters AS03 and AS10 are connected with a multiplexer AS13 to provide an XOR gate in ASUBCONT cell that corresponds to XOR gate 52 in control cell 142 of FIG. 8. This XOR gate responds to carry-in supplied via connection cI from the adjoining bit-slice operation cell ASUBSLICEl and to the signal supplied in non-complemented and complemented form via lines EQ and NEQ to XOR the carry-in and EQ-line signals on line LT. An inverter AS11 complements the signal on line LT on line GE. One of these signals is applied (by one of two optional interconnection patterns) to the RIN line to be latched by latch element AS02 to be supplied on output connections GELT.

A multiplexer AS12 in ASUBCONT cell corresponds to multiplexer 48 in the FIG. 8 control cell 142. The output signal from multiplexer AS12 is buffered by the cascaded inverter AS17 and AS00 to drive carry return line CR. Delay block 56 of control cell 142 finds no correspondence within ASUBCONT cell itself, the multiplexer AS12 being controlled by CONTROLLSD signal as complemented by an inverter AS16 and complemented again by an inverter AS15. Delay block 56 is inserted outside ASUBCONT cell automatically by the silicon compiler making an actual circuit design, as part of its programming to generate proper system timing. Multiplexer AS12 selects either delayed carry-in from delay element AS01 or a forced carry-in CARRYLOW as twice-complemented by cascaded inverter amplifiers AS14 and AS20.

While only certain preferred features of the invention have been herein described and illustrated, many modifications and changes will occur to those skilled in the art and acquainted with the foregoing disclosure. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the invention. 

What is claimed is:
 1. In a particular portion of a state-variable electronic apparatus employing an efficient digit-serial arithmetic and being supplied recurring clockwise signals to advance data in parallel with other portions of said state-variable electronic apparatus, each digit-serial operand employed in the digit-serial arithmetic of said particular portion of the state-variable electronic apparatus having data words invariably of W bits supplied n bits at a time in W/n successive digits of progressively grater significance, where n is an integer at least three and W is a multiple at least twice of n, the bits in each succeeding digit of each successive data word of each said digit-serial operand being identified by respective ones of consecutive ordinal numbers first through n^(th) in order of their increasing significance, the n^(th) bit of the last digit of each data word being indicative of its sign when that said data word is a signed number, a combination comprising:first, second and third n-bit-wide data latches arranged for simultaneously latching responsive to each of said clocking signals to advance data, each said data latch comprising a respective plurality n in number of unit-clock delay elements identified by respective ordinal numbers first through n^(th) and provided with respective input connections and respective output connections; means for applying a stream of first digit-serial operands to the respective input connections of the first through n^(th) unit-clock delay elements in said first n-bit-wide data latch; means for applying a stream of second digit-serial operands to the respective input connections of the first through n^(th) unit-clock delay elements in said first n-bit-wide data latch so the least significant digit of each said second digit-serial operand has its n bits latched at the respective output connections of the first through n^(th) unit-clock delay elements in said second n-bit-wide data latch at the same time as the least significant digit of a corresponding one of said first digit-serial operands has its n bits latched at the respective output connections of the first through n^(th) unit-clock delay elements in said first n-bit-wide data latch; a plurality n in number of full adders identified by respective ordinal numbers first through n^(th), each full adder provided with a respective addend input connection connected from the output connection of the unit-clock delay element identified by corresponding ordinal number in said first n-bit-wide data latch, a respective augent input connection connected from the output connection of the unit-clock delay element identified by corresponding ordinal number in said second n-bit-wide data latch, a respective carry input connection, a respective sum output connection connected to the input connection of the unit-clock delay element identified by corresponding ordinal number in said third n-bit-wide data latch, and a respective carry output connection, the carry output connection of each of said full adders except the n^(th) respectively connecting to the carry input connection of said full adder identified by the next higher ordinal number; and selection apparatus for selecting a forced carry bit to the carry input connection of sad first full adder during said times the first digits of said first and second digit-serial operands are latched and for otherwise selecting the bits supplied at the carry output connection of said n^(th) full adder as delayed one clock interval to the carry input connection of said first full adder.
 2. The combination set forth in claim 1 wherein W/n is greater than three.
 3. In a particular portion of a state-variable electronic apparatus employing an efficient digit-serial arithmetic and being supplied recurring clocking signals to advance data in parallel with other portions of said state-variable electronic apparatus, each digit-serial operand employed in the digit-serial arithmetic of said particular portion of the state-variable electronic apparatus having data words invariably of W bits supplied n bits at a time in W/n successive digits of progressively greater significance, where n is an integer at least three and W is a multiple of at least twice of n, the bits in each successive digit of each successive data word of each said digit-serial operand being identified by respective ones of consecutive ordinal numbers first through n^(th) inn order of their increasing significance, a combination comprising:first, second and third n-bit-wide data latches arranged for simultaneously latching responsive to each of said clocking signals to advance data, each said data latch comprising a respective plurality n in number of unit-clock delay elements identified by respective ordinal numbers first through n^(th) and provided with respective input connections and respective output connections; means for applying a stream of first digit-serial operands to the respective input connections of the first through n^(th) unit-clock delay elements in aid first n-bit-wide data latch; means for applying a stream of second digit-serial operands to the respective input connections of the first through n^(th) unit-clock delay elements in said second n-bit-wide data latch so the least significant digit of said second digit-serial operand has its n bits latched at the respective output connections of the first through n^(th) unit-clock delay elements in said second n-bit-wide data latch at the same times as the least significant digit of said first digit-serial operand has its n bits latched at the respective output connections of the first through n^(th) unit-clock delay elements in said first n-bit-wide data latch; a plurality n in number of full adders identified by respective ordinal numbers first through n^(th), each full adder provided with a respective addend input connection connected from the output connection of the unit-clock delay element identified by corresponding ordinal number in said first n-bit-wide data latch, a respective augend input connection, a respective carry input connection, a respective sum output connection connected to the input connection of the unit-clock delay element identified by corresponding ordinal number in said third n-bit-wide data latch, and a respective carry output connection, the carry output connection of each of said full adders except the n^(th) respectively connecting to the carry input connection of said full adder identified by the next higher ordinal number; selection apparatus for selecting a forced carry bit to the carry input connection of said first full adder during said times the first digits of said first and second digit-serial operands are latched and for other selecting the bits supplied at the carry output connection of said n^(th) full adder as delayed one clock interval too the carry input connection of said first full adder; and means for selectively one's complementing the bits from the output connections of said first through n^(th) unit-clock delay elements in said second n-bit-data latch, for application to the augend input connections of said first through n^(th) full adders respectively.
 4. The combination set forth inn claim 3 wherein W/n is greater than three. 